Design a mod-6 (3-bit) counter using only structural code constructs, flip-flops, and Verilog primitive gates. Each student is to implement their design with the configuration of flip-flops and count sequence 7 5 3 2 4 1. The counter should be self-starting after reset from a count value of 7 (seven). All unused states should transition to the reset value. Do Not use any Boolean operators from the Verilog language.Flip-flop order: D, JK, T

1.(a) Using JK flip-flops, design a MOD-12 synchronous counter, For full credit your circuit must be drawn clearly, legibly and labeled. Include a state-diagram of this counter.(b) Explain the difference between a ripple counter and a synchronous counter.